Successive approximation register (SAR) analog-to-digital converters (ADC) perform analog to digital conversions. The SAR ADC includes a number of different components including comparators.
FIG. 1 illustrates a conventional comparator configuration within a SAR ADC. A conventional SAR ADC 100 includes an analog input, a sample and hold amplifier 105, a digital-to-analog converter (DAC) 110, a comparator 120, and logic 130. The comparator 120 includes a pre-amplifier 123, a delay device 125 and latch 127. The pre-amplifier 123 amplifies the input signals and outputs the amplified input signal to the latch, improving the input referred noise and linearity of the comparator. In order to allow the preamplifier 123 time to amplify the input signal, a control signal RESET is delayed before going to the latch, so that the latch is held in a known reset state while the preamplifier is amplifying. Once the delayed reset signal is released, the latch will regenerate and the comparator makes it decision. The delay of the delay device 125 is fixed by inserting an inverter or series of inverters in the circuit path. A delayed output signal DEL_RESET from the delay device 125 is provided to the latch 127. FIG. 2 illustrates an exemplary timing diagram of a conventional comparator, such as comparator 120.
Typically, as shown, by the preamplifier output 230, the preamplifier 123 operates for some period of time (t1 to t2) before the latch 127 is released. The maximum speed of a SAR ADC 100 is dependent upon the operating speed of the digital logic and switches such as those that form the comparator 120. The operating speed of the digital logic and switches, e.g., inverters and latches, vary in response to various circuit conditions such as variations in the supply voltage, variations in temperature, or fabrication process variations across different manufacturing lots of integrated chips. Examples of fabrication process parameters may be device characteristics, such as threshold voltage and oxide thickness.
When the delay through the delay elements 125 becomes shorter because of the faster operating conditions, such as rises in circuit temperature, supply voltage increases, process effects, or other conditions, the signal DEL_RESET 220 may be output sooner. Consequently, the preamplifier 123 has less time to amplify before the latch 127 is released, as shown by 240. However, the increased comparator 120 operating speed due to the change in parameters is generally lost because the sample rate of the ADC is typically held constant. In other words, the preamplifier 123 and latch 127 within the comparator 120 may finish operating sooner on a given input, but ultimate output of the latch signal still has to wait until the end of the sampling period because the ADC is still clocked at the sampling rate, which remains unchanged.
The inventor has recognized the benefit of a device that operates opposite to the effects of PVT variations. An exemplary implementation of an application of the device is for a comparator in a SAR ADC that adaptively adjusts its timing to take advantage of changes in conditions and circuit parameters to provide better performance. For example, it would be beneficial if, as the digital logic and switching speeds increase, the delay between amplifying the input signal and releasing the latch adaptively changed to allow the preamplifier or latch more time to operate on the input signal to fill the sampling period. This provides the advantage of better signal-to-noise ratios and/or lower power.